1 module count#(parameter N=8)(
 2 input clk,
 3 input clear,
 4 output[N-1:0] cnt_Q
 5 );
 6 reg[N-1:0] cnt;
 7 assign cnt_Q = cnt;
 8 
 9 always@(posedge clk)
10   if(clear)
11     cnt <= 'h0;      //同步清 0，高電平有效
12   else
13     cnt <= cnt+1'b1; //加法計(jì)數(shù)
14 
15 endmodule

always@(posedge clk)
    if(clear)
        cnt <=  'h0;    //同步清 0，高電平有效
    else if(cnt==K)
        cnt <= 'h0;
    else
        cnt <= cnt+1'b1; //減法計(jì)數(shù)            

 1 module updown_count#(parameter N=8)(
 2     input clk,
 3     input clear,
 4     input load,
 5     input up_down,
 6     input [N-1:0] preset_D,
 7     output[N-1:0] cnt_Q
 8 );
 9 reg[N-1:0] cnt;
10 assign cnt_Q = cnt;
11 
12 always@(posedge clk)
13   if(clear)
14     cnt <= 'h0;      //同步清 0，高電平有效
15   else if(load)
16     cnt <= preset_D; //同步預(yù)置
17   else if(up_down)
18     cnt <= cnt+1;    //加法計(jì)數(shù)
19   else
20     cnt <= cnt-1;    //減法計(jì)數(shù)
21 
22 endmodule

 1 module test#(parameter N=3)(
 2 input clk,
 3 input rst_n,
 4 output clk_div
 5 );
 6 
 7 reg [N-1:0] div_reg        ;//分頻計(jì)數(shù)器
 8 always @(posedge clk or negedge rst_n)
 9     if (rst_n == 1'b0 )
10         div_reg    <= 0 ;
11     else 
12         div_reg    <= div_reg + 1'b1 ;
13 
14 assign clk_div = div_reg[N-1] ;
15 
16 
17 endmodule

 1 module test#(parameter N=3)(
 2 input clk,
 3 input rst_n,
 4 output clk_div
 5 );
 6 
 7 reg [N-1:0] div_reg        ;//分頻計(jì)數(shù)器
 8 always @(posedge clk or negedge rst_n)
 9     if (rst_n == 1'b0 )
10         div_reg    <= 0 ;
11     else if(div_reg == 3'd4)//從0計(jì)數(shù)到4，然后返回到0,5分頻
12         div_reg    <= 0;
13     else
14         div_reg    <= div_reg + 1'b1 ;
15 
16 assign clk_div = div_reg[N-1] ;
17 
18 
19 endmodule

 1 module test#(parameter N=6)(
 2 input clk,
 3 input rst_n,
 4 output clk_div
 5 );
 6 reg div_reg ;
 7 reg [N-1:0] div_cnt        ;//分頻計(jì)數(shù)器
 8 always @(posedge clk or negedge rst_n)
 9     if (rst_n == 1'b0 )begin
10         div_cnt    <= 0 ;
11         div_reg    <= 0 ;
12     end 
13     else if(div_cnt == (N/2 - 1))begin
14         div_cnt    <= 0;
15         div_reg    <= ~div_reg ;
16     end 
17     else
18         div_cnt    <= div_cnt + 1'b1 ;
19 
20 assign clk_div = div_reg ;

 1 module test#(parameter N=3)(//N分頻，這里是3分頻
 2 input clk,
 3 input rst_n,
 4 output clk_div
 5 );
 6 
 7 reg [N-1:0] div_cnt        ;//分頻計(jì)數(shù)器
 8 reg div_reg ;
 9 always @(posedge clk or negedge rst_n)begin
10     if (rst_n == 1'b0 )begin
11         div_cnt    <= 0 ;
12         div_reg        <= 1 ;
13     end else if (div_cnt == (N-1)/2)begin//計(jì)數(shù)到(N-1)/2，進(jìn)行翻轉(zhuǎn)和繼續(xù)計(jì)數(shù)
14         div_reg        <= ~div_reg;
15         div_cnt    <= div_cnt + 1'b1 ;
16     end else if ( div_cnt == (N-1) )begin//計(jì)數(shù)到N-1，進(jìn)行清零和翻轉(zhuǎn)
17         div_cnt        <= 0 ;
18         div_reg        <= ~div_reg;
19     end else 
20         div_cnt    <= div_cnt + 1'b1 ;
21         
22 end         
23 assign clk_div = (N == 1)?clk:div_reg ;//注意這里
24 
25 
26 endmodule

 1 module test#(parameter N=5)(//N分頻
 2 input clk,
 3 input rst_n,
 4 output clk_div
 5 );
 6 
 7 reg sig_r ;//定義一個(gè)上升沿翻轉(zhuǎn)的信號(hào)
 8 reg sig_f ;//定義一個(gè)下降沿翻轉(zhuǎn)的信號(hào)
 9 reg [N-1:0]    cnt_r;//上升沿計(jì)數(shù)器
10 reg [N-1:0]    cnt_f;//下降沿計(jì)數(shù)器
11 
12 wire clk_f ;
13 assign clk_f = ~clk ;//用來(lái)觸發(fā)下降沿計(jì)數(shù)器的時(shí)鐘
14                     //由于同時(shí)使用上升沿和下降沿觸發(fā)器不好，因此我們?yōu)橥贿呇?，都使用上升沿觸發(fā)
15                     //只不過(guò)是將時(shí)鐘進(jìn)行反向
16                     
17 always @(posedge clk or negedge rst_n)begin//上升沿計(jì)數(shù)
18     if(rst_n == 1'b0)begin
19         sig_r    <= 0 ;
20         cnt_r    <= 0 ;
21     end else if( cnt_r == (N-1)/2 )begin
22         sig_r    <= ~sig_r ;
23         cnt_r    <= cnt_r + 1 ;
24     end else if ( cnt_r == (N-1) )begin
25         sig_r    <= ~sig_r ;
26         cnt_r    <= 0 ;
27     end else 
28         cnt_r    <= cnt_r + 1 ;
29 end                     
30 
31 always @(posedge clk_f or negedge rst_n)begin//下降沿計(jì)數(shù)
32     if(rst_n == 1'b0)begin
33         sig_f    <= 0 ;
34         cnt_f    <= 0 ;
35     end else if( cnt_f == (N-1)/2 )begin
36         sig_f    <= ~sig_f ;
37         cnt_f    <= cnt_f + 1 ;
38     end else if ( cnt_f == (N-1) )begin
39         sig_f    <= ~sig_f ;
40         cnt_f    <= 0 ;
41     end else 
42         cnt_f    <= cnt_f + 1 ;
43 end 
44 
45 assign clk_div = sig_f || sig_r ;
46                     
47 endmodule

 1 module test #( parameter cfactor= 5)(
 2   input clk,
 3   input rst_n,
 4   output clk_div
 5 );
 6 reg clk_loc;
 7 //reg [15:0] cnt;//allowed maximum clock division factor is 65536
 8 reg [7:0] cnt;//allowed maximum clock division factor is 256
 9 
10 assign clk_div = (cfactor==1)? clk : clk_loc;
11 //assign clk_div = ((rst==1) || (cfactor==1))? clk : clk_loc;
12 
13 always@(posedge clk or negedge rst_n)
14   if(!rst_n)begin
15     cnt <= 'd0;
16     clk_loc = 1;
17   end
18   else begin
19     cnt <= cnt + 1'b1;
20     if(cnt==cfactor/2-1)
21       clk_loc = 0;
22     else if(cnt==cfactor-1) begin
23       cnt <= 'd0;
24       clk_loc = 1;
25     end
26   end
27 
28 endmodule

 1 module test#(parameter N=1)(//N分頻
 2 input clk,
 3 input rst_n,
 4 output clk_div
 5 );
 6 
 7 //奇數(shù)分頻
 8 reg sig_r ;//定義一個(gè)上升沿翻轉(zhuǎn)的信號(hào)
 9 reg sig_f ;//定義一個(gè)下降沿翻轉(zhuǎn)的信號(hào)
10 reg [N-1:0]    cnt_r;//上升沿計(jì)數(shù)器
11 reg [N-1:0]    cnt_f;//下降沿計(jì)數(shù)器
12 
13 wire clk_f ;
14 assign clk_f = ~clk ;//用來(lái)觸發(fā)下降沿計(jì)數(shù)器的時(shí)鐘
15                     //由于同時(shí)使用上升沿和下降沿觸發(fā)器不好，因此我們?yōu)橥贿呇?，都使用上升沿觸發(fā)
16                     //只不過(guò)是將時(shí)鐘進(jìn)行反向
17                     
18 always @(posedge clk or negedge rst_n)begin//上升沿計(jì)數(shù)
19     if(rst_n == 1'b0)begin
20         sig_r    <= 0 ;
21         cnt_r    <= 0 ;
22     end 
23     else begin
24         cnt_r    <= cnt_r + 1 ;
25         if( cnt_r == (N-1)/2 )begin
26             sig_r    <= ~sig_r ;
27         end else if ( cnt_r == (N-1) )begin
28             sig_r    <= ~sig_r ;
29             cnt_r    <= 0 ;
30         end 
31     end 
32 end                     
33 
34 always @(posedge clk_f or negedge rst_n)begin//下降沿計(jì)數(shù)
35     if(rst_n == 1'b0)begin
36         sig_f    <= 0 ;
37         cnt_f    <= 0 ;
38     end 
39     else begin
40         cnt_f    <= cnt_f + 1 ;
41         if( cnt_f == (N-1)/2 )begin
42             sig_f    <= ~sig_f ;
43         end else if ( cnt_f == (N-1) )begin
44             sig_f    <= ~sig_f ;
45             cnt_f    <= 0 ;
46         end 
47     end     
48 end 
49 
50 //偶數(shù)分頻
51 reg div_reg ;
52 reg [N-1:0] div_cnt        ;//分頻計(jì)數(shù)器
53 always @(posedge clk or negedge rst_n)begin
54     if (rst_n == 1'b0 )begin
55         div_cnt    <= 0 ;
56         div_reg    <= 0 ;
57     end 
58     else begin
59         div_cnt    <= div_cnt + 1'b1 ;
60         if(div_cnt == (N/2 - 1))begin
61             div_cnt    <= 0;
62             div_reg    <= ~div_reg ;
63         end 
64     end
65 end        
66 assign clk_div = (N == 1)?clk:
67                 ( N%2 == 1)?(sig_f || sig_r ): div_reg;//這里用來(lái)輸出分頻值。對(duì)2的取余操作是綜合的
68                     
69 endmodule