1.Verilog HDL information at xxx.v:always construct contains both blocking and non-blocking assignments
在一個always塊中同時使用了阻塞和非阻塞賦值。

2.Warning: Parallel compilation is not licensed and has been disabled
并行編譯未獲得許可，已經(jīng)終止。

3.Warning (10227): Verilog HDL Port Declaration warning at v_led.v(4): data type declaration for "out" declares packed dimensions but the port declaration declaration does not
應該在聲明引腳輸入輸出時就寫明位寬，否在之后聲明就會出現(xiàn)以上錯誤。如output out；reg[7:0] out；就會報警告，應該寫成output reg[7:0] out;才正確。

4.Warning (10230): Verilog HDL assignment warning at v_led.v(13): truncated value with size 32 to match size of target (8)
原因:在HDL設計中對目標的位數(shù)進行了設定,如:reg[4:0] a;而默認為32位,將位數(shù)裁定到合適的大小
措施:如果結果正確,無須加以修正,如果不想看到這個警告,可以改變設定的位數(shù)

5.Warning: Found 9 output pins without output pin load capacitance assignment
 輸出引腳沒用輸出引腳負載電容。

6.Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
警告：保留所有未使用引腳的設置還沒有被指定，并且將默認“作為驅(qū)動輸出的‘地’”。

7.Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
警告：跳過模塊“PowerPlay功耗分析儀”，由于分配FLOW_ENABLE_POWER_ANALYZER

8.Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
這個是比較詭異的警告，在網(wǎng)上搜了半天，沒有確切的解決辦法，這個信息大致的意思是未定義管腳設置接地，其實無關緊要，但是放在那不管很影響我的0warning記錄，于是在setting里面找，后來發(fā)現(xiàn)在device里有個對話框device and pin options，打開后里面有個unused pins，把里面的選項由原來的接地改成三態(tài)，再仿真警告就沒了，但奇怪的是，后來我又改了回來，再仿真，警告還是沒有出現(xiàn)，不知何故。

9.Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF
這個是說時鐘延遲的一個設置應該設置為ON，網(wǎng)上都說沒什么影響，貌似與時序仿真有關，不太清楚，設置在Classic Timing Analyzer中有個more setting，里面下拉菜單中就有ENABLE_CLOCK_LATENCY，設置為ON就OK。
PS：問題

How do I run the PowerPlay Power Analyzer automatically during compilation?
解決方案

In the Quartus? II software, you can enable the PowerPlay Power Analyzer to run automatically during compilation by adding the following assignment to your Quartus II Settings File (.qsf):

set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
This assignment is scheduled to be available in the Settings dialog box in a future release of the Quartus II software.

10.在Nios II中編譯時有如下提示warning: no newline at end of file
在最后的一個大括號外再加一個回車。